The present invention relates to a bipolar transistor used in various semiconductor integrated circuits or the like and a method of manufacturing the same and, more particularly, to a vertical bipolar transistor and a method of manufacturing the same.
A typical example of a conventional high-density, high-speed bipolar transistor for a semiconductor IC as described in Electronics Letter, Vol. 19, No. 8, PP. 283-284, Apr. 14, 1983 is illustrated in FIG. 27. Referring to FIG. 27, reference numeral 1 denotes a p.sup.- -type silicon substrate; 2, an n-type epitaxial layer constituting a collector region; 3, an n.sup.+ -type buried layer; 4A to 4E, oxide films; 5, a p.sup.+ -type channel cut layer; 6, a base region; 7, a base contact region; 8, an emitter region; 9, an intrinsic transistor region (the region surrounded by a broken line); 10, a base metal electrode; 11, an emitter metal electrode; 12, a collector metal electrode; 13, a polysilicon electrode layer doped with a p-type impurity; 14A and 14B, polysilicon electrode layers containing an n-type impurity; and 15, a nitride film.
With the structure in FIG. 27, the region 9 is the region indispensable to transistor operation. Formation of the base, collector and emitter electrodes constituted by polysilicon layers at positions near the region 9 decreases parasitic capacitances and resistances. However, when isolation of the electrodes and mask alignment margins are taken into consideration, the actual transistor size is larger than the region 9. The 1-.mu.m rule is applied to the example in FIG. 27. Although the emitter electrode constituted by the polysilicon layer 14A and the base electrode constituted by the polysilicon layer 13 are self-aligned and formed on the substrate surface adjacent to each other without degrading transistor characteristics, the distance between the emitter and collector electrodes cannot be decreased since it is determined by a photolithographic pattern rule during formation of the underlying films prior to the formation of electrodes. Both the junction capacitance between the p.sup.- -type silicon substrate 1 and the n.sup.+ -type buried layer 3, serving as the collector region, and the area occupied by the transistor as a whole are increased. High-speed operation and high density cannot be achieved. In order to form vertical npn and pnp transistors on a single substrate to prepare a complimentary bipolar transistor in the same manner as the vertical npn transistor in FIG. 1, a complicated fabrication process is required. On the other hand, if the npn and pnp transistors are constituted by vertical and lateral transistors, respectively, the electrical characteristics of the pnp transistor are poor.